1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device having an error check bit memory region. More specifically, the invention relates to a structure for repairing a defective bit of a semiconductor memory device.
2. Description of the Background Art
In semiconductor memory devices that can carry out data input/output in the unit of a plurality of bits, there are some that can carry out input/output of data together with an error checking bit. An error checking bit is used for detecting whether there is an error in data bits forming the data. Parity check is one method of checking an error.
According to a parity check method, the value of a parity bit of 1 bit is defined as "1" or "0" according to whether the number of ones in the data bits forming the data is an even number or an odd number, and the parity bit is added to the data bits. The data arrangement of data bits and a parity bit is defined so that the number of ones is constantly an even number or an odd number. The data bits and a parity bit are received at the time of data transfer in a data communication system, for example, to detect the number of ones included in the data arrangement, whereby an error of 1 bit in the data bits that are being transferred is detected.
FIG. 16 shows a structure of a memory array of a conventional semiconductor memory device. In FIG. 16, an example of a structure of a dynamic random access memory that can input and output 9 bits of information I/O0 to I/O8 at a time is illustrated. This dynamic random access memory has a x9 organization where a parity bit of 1 bit is added to a x8 organization.
Referring to FIG. 16, a semiconductor memory device 100 includes pads 6a, 6b, 6c, 6d, 6e, 6f, 6g, 6h and 6i for receiving in parallel 9 bits of information I/O0-I/O8, and memory cell array blocks 3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h and 3i provided corresponding to pads 6a-6i. In the following description, the 8 bits of I/O0 to I/O7 are referred to as data bits, and I/O8 is referred to as the parity bit.
Spare rows of 4a-4i and spare columns of 5a-5i for repairing a defective bit are provided for each of memory cell array blocks of 3a-3i, respectively.
Row decoders 1a-1i are provided for memory cell blocks 3a-3i, respectively, for decoding a supplied address signal to select one row (word line) in a corresponding memory cell array block. A column decoder 2a is provided for memory cell blocks 3a-3d for selecting 1 column from each memory cell array block according to a supplied column address signal. A column decoder 2b is provided to memory cell array blocks 3e-3i for decoding a supplied column address signal to select a column from each of memory cell array blocks 3e-3i.
Row decoders 1a-1i respectively include a spare row decoder, and column decoders 2a and 2b respectively include a spare column decoder. When a supplied address designates a defective row (or column), a spare row (column) decoder inhibits the selection of that defective row (or column) and carries out the selection of 1 row (or 1 column) in the spare rows (or columns). In the following description, the row decoder for selecting a spare row 4 (indicating spare rows 4a-4i generally) is called the spare row decoder, and the decoder for selecting a spare column 5 (indicating spare columns 5a-5i generally) is called the spare column decoder, and the decoders for selecting rows and columns in a memory cell array block 3 (indicating blocks 3a-3i generally) are called the normal row decoder and the normal column decoder.
Memory cell array blocks 3a-3d are connected to pads 6a-6d, respectively, via a data bus 40a. Memory cell array blocks 3e-ei are connected to pads 6e-6i, respectively, via a data bus 40b. Although not shown, an input/output circuit for carrying out buffering of input and output signals are provided respectively for memory cell array blocks 3a-3i. Data buses 40a and 40b are provided between pads 6a-6i and the input/output circuit carrying out such a buffering process. Array blocks 3a-3i and pads 6a-6i have a one-to-one correspondence.
A spare row and a spare column are provided respectively for memory cell array blocks 3a-3i. There may exist a memory cell that does not operate properly in a certain memory cell array block 3 on account of admixture of particles during the manufacturing process of the device or defect in the silicon substrate itself. A row or column including the defective memory cell that does not operate properly is replaced by spare row 4 or spare column 5. By replacing the defective memory cell with a spare memory cell, the defective memory cell in the memory cell array block can be repaired. Thus, the required number of memory cells that properly operate can be ensured in a memory cell array block even if there is a defective memory cell in a certain memory cell array block.
A conventional semiconductor memory device has a spare row 4 and a spare column 5 provided in respective I/O blocks. In the following description, an I/O block is assumed to indicate a circuit block associated with 1 bit. An I/O block includes a memory cell array block, a spare row, a spare column, a row decoder, and an input/output buffer circuit (not shown in FIG. 16).
Replacement of a defective memory cell is carried out independently in each I/O block. For example, a defective memory cell in memory cell array block 3a can be substituted by only spare row 4a or spare column 5a. If defective memory cells are intensive in a certain I/O block, they may not be completely substituted with the spare row 4 and the spare column 5 provided in that I/O block. A semiconductor memory device including such a defective I/O block has been treated as a condemned product since it cannot properly operate as a semiconductor memory device of x9 configuration. This generates a problem that the production yield cannot be improved.
If there is a defective I/O block in a semiconductor memory device of x9 organization, a possible consideration is to use that semiconductor memory device as a x8 organization device without using that defective I/O block. However, the position of the defective I/O block cannot be predicted. The connection between an I/O block and a pad for signal input/output is determined uniquely. Therefore, when using that semiconductor memory device as one of a x8 organization, the position of the unusable pad cannot be predicted.
As shown in FIG. 17, a package 600 accommodating semiconductor memory device 100 is provided with external terminals 60a-60i. Pads 6a-6i of semiconductor memory device 100 are connected to external terminals 60a-60i via bonding wires.
The connection between pads 6a-6i and external terminals 60a-60i is determined uniquely and fixedly. The position/arrangement of data input/output terminals 60a-60i of external terminals is defined in one-to-one correspondence in the specification. If there is defective input/output block in a semiconductor memory device of a conventional structure, it cannot be re-used as a semiconductor memory device of x8 organization. This is because the position of the usable data input/output terminals differ from product to product.